1. Field of the Invention
This invention relates generally to semiconductor devices, and more specifically, to a system and method for reducing leakage current in a semiconductor device by providing reduction control circuitry in accordance with a probability determination.
2. Discussion of the Prior Art
Two main approaches have been proposed for reducing leakage currents: threshold voltage control, and logic state control.
Since leakage current in integrated circuits is inversely proportional to the threshold voltage of FETs, raising the threshold voltage may reduce leakage current. However, raising the threshold voltage also decreases the performance of the device. Therefore, passive threshold voltage control methods typically comprise selecting a portion of the non-timing critical logic paths, and using higher threshold devices for that portion of the circuit. Active threshold control methods also exist in which the threshold voltage is dynamically adjusted by active body or well biasing when the chip is in a xe2x80x9cstand-byxe2x80x9d or xe2x80x9csleepxe2x80x9d mode where full-performance is not required of the circuit and minimum leakage is desired.
Logic state control for leakage is based on the concept that a circuit""s leakage is highly dependent on the state of its inputs. For example, a CMOS two-way NAND gate may have an order of magnitude less leakage current when both inputs are at a low voltage than when they are both at a high voltage. Leakage control in these methods consists of finding a set of logic values which, when applied to a logic network at its inputs, produces the lowest leakage state possible given the logic network. The set of logic values that causes this xe2x80x9clow leakage statexe2x80x9d may be called the xe2x80x9clow leakage vectorxe2x80x9d. The low leakage vector is applied to the network when the chip enters the xe2x80x9cstand-byxe2x80x9d or xe2x80x9csleepxe2x80x9d modes of operation, by means of modified storage elements which force the low leakage vector onto the network.
One of the main challenges with this approach is finding the low leakage vector on large logic circuits. Since the number of possible logic states is directly proportional to the number of inputs to the circuit, it is impractical, if not impossible, to exhaustively check all possible states. Thus, heuristic algorithms have been developed to explore the state space and find xe2x80x9clow leakage vectorsxe2x80x9d. These algorithms are limited by the fact that they can only control the inputs to the circuit and thus will likely not find the xe2x80x9clowest leakage vectorxe2x80x9d possible.
Another limitation of the logic state control approach is that the distinction between xe2x80x9csleepxe2x80x9d and xe2x80x9cactivexe2x80x9d states is not always clear. Different parts of the design will be inactive (i.e., in a sort of xe2x80x9csleepxe2x80x9d mode) for different amounts of time. In new technologies where the relative importance of leakage power relative to active switching power is increasing, reducing leakage of these inactive portions of the network becomes important even for relatively short periods of time.
In previous systems, leakage reduction techniques have focused on statically determining a low leakage vector that can be applied to the design upon entering a xe2x80x9cstandbyxe2x80x9d state, by means of forcing the storage elements to the low leakage vector.
There are techniques in the art that utilizes probabilistic information about the network state for optimizing digital circuit design. One reference in particular by S. Sirichotiyakul, T. Edwards, et al. entitled xe2x80x9cStand-by Power Minimization through Simultaneous Threshold Voltage Selection and Circuit Sizingxe2x80x9d. ACM 1999, Ch. 26.2, pp. 436-441. Specifically, this reference teaches that a probabilistic analysis may be used to size transistors and change voltage thresholds in order to reduce or minimize leakage. However, this prior art reference is not concerned with the circuit sleep state nor is it concerned with the setting of the logic state of signals in order to minimize leakage.
It would therefore be highly desirable to provide improved methods and mechanisms for finding a low leakage vector by using probabilistic approaches to find the expected leakage of integrated circuit devices at any point in time, based on logic state statistics.
It would therefore be highly desirable to provide an improved method and mechanism that allows manipulation of logic that results in changes to the probabilities so that the circuit may be in an optimized state, either globally or locally, when the semiconductor circuit is in an idle condition.
Furthermore, it would be highly desirable to provide improved methods and mechanisms for finding a low leakage vector by using probabilistic approaches that permit logic optimization for reducing leakage current even while the circuit is xe2x80x9cactivexe2x80x9d, thus accommodating the indistinct line between xe2x80x9csleepxe2x80x9d and xe2x80x9cactivexe2x80x9d mode operation.
It is an object of the present invention to provide a logic system design methodology that forces the states of logic gates based on a probabilistic analysis in order to reduce the leakage.
It is a further object of the present invention to provide a method and mechanism for finding leakage probabilities during synthesis to modify the network such that it results in a lower leakage design during any of the many active/semi-active/standby states.
It is another object of the present invention to provide a logic system design methodology implementing a probabilistic analysis for reducing the leakage during any of the many active/semi-active/standby states without making device accommodations, or adding special switches, to result in a lower overhead.
It is yet another object of the present invention to provide a method and mechanism for forcing the logic states exploiting the intrinsic nature of the gates during synthesis to modify the network such that it results in a lower leakage design.
The present invention overcomes the difficulty of finding the exact low leakage vector by using probabilistic approaches to find the expected leakage at any point in time, based on logic state statistics. This enables logic optimization to reduce leakage current even while the circuit is xe2x80x9cactivexe2x80x9d, thus accommodating the indistinct line between xe2x80x9csleepxe2x80x9d and xe2x80x9cactivexe2x80x9d mode operation. The probabilistic information may be computed and stored by several techniques not unlike those techniques used to determine switching information for analysis of switching power. Information may be gathered on individual nets as a result of a simulation trace. Alternatively, the probabilities of various input states (sets of primary input and latch output logical values) may be tracked in order to keep track of correlations between signals. Such input state information may be stored compactly using binary decision diagrams (BDDs) or other well-known means. Given for each signal the probability of that signal being at a particular value (either independent of all other signal values or correlated through state information) and information for each block in the logic network about the leakage of that block for each possible combination of input values, the estimated leakage power may be computed by summing over all blocks: the sum over all combinations of block input values of the leakage under that combination of input values multiplied by the probability of occurrence of that combination of input values. As changes are made to the logic network which affect these signal probabilities, the probabilities may be updated and the resulting change in leakage power may be estimated. The signal probability updates may be achieved by re-simulating part or all of the logic network, by recomputing probabilities on nets in the fanout cone of logic changes based on updated probabilities at the inputs of the gates driving the nets, by some combination of these, or by other means.
Along with signal probabilities, and in a similar manner, there is computed, for each state, the probability that any given signal net will switch when the network is in that state. Again, this may be done by treating the various nets in the network independently in which case the switching probabilities of interest are merely the conditional probability that the net will go high given that it is low, and the conditional probability that the net will go low given that it is high. These switching probabilities may also be computed based on global states using BDDs or by other means. This information will be used to determine the relative importance of reducing leakage on the net, by helping determine how long the net is likely to be in a particular state and thus dissipate the leakage power associated with that state.
When significantly distinct modes of operation are known, separate sets of probabilities and consequent leakage power estimates may be maintained for each mode. Optimizations may then be implemented to reduce a weighted sum of these different mode powers based on the expected periods spent in each mode and the importance of power reduction in each mode (for example, a device operating on either battery power or wall power will need to reduce power more in the former mode than in the latter). Note that in some modes, certain logic network input values (primary inputs or latch outputs) will be known and will, therefore, have state probabilities of zero and one. Even though the value of a primary input cannot be controlled, a particular mode may be defined as one in which a particular primary input is in a defined state.
Given this probabilistic leakage information, a variety of optimizations to reduce leakage power is performed. Generally, these methods will take advantage of xe2x80x9cdon""t carexe2x80x9d states in the logic, i.e., conditions at the input to a gate or sub-network for which it does not matter what the gate or sub-network output values are. These don""t care conditions may be determined through specifications in the high level language input (e.g., a default case in a case statement), through analysis of the logic network, or by a combination of these. Similarly, the logical conditions under which particular nets or sets of nets are don""t cares may similarly be determined by some specified signal (e.g., a xe2x80x9csleep modexe2x80x9d signal for the particular function or for the entire chip), by an analysis of the logic network (i.e., determination of the logical function which implies a don""t care), or a combination of these. Note that the entire don""t care function does not have to be used in the optimizations (i.e., changes do not have to be made for all don""t care conditions which reduce the leakage), as long as the function chosen to determine when changes may be made always means that the signal is a don""t care. In other words, functions are sought which are sufficient to determine that the signal is a don""t care, but which need not be necessary for it. Additionally, it should be noted that there may be an interaction between the don""t care functions and the leakage associated with a particular net. For example, a signal may be a don""t care, both in some mode A in which increasing the signal probability decreases leakage and in some mode B in which decreasing the signal probability decreases leakage. Obviously, it is an objective to make changes which drive the signal probability in different directions in these two modes.
According to the invention, there is provided a method for reducing leakage power of a logic network comprising a plurality of nets, comprising the steps of: determining observability don""t care (ODC) information for one or more nets in said logic network, the ODC information representing a set of inputs for which an input value at the net has no influence on an output value of the logic network, the ODC being used for identifying sleep states for individual nets of the logic network; performing a simulation to force the nets to a particular value during at least a portion of a sleep state and performing a probabilistic analysis to determine at least one net in which expected power consumption will be reduced; and forcing the determined net to the value determined for the portion of that sleep state when expected power consumption is reduced.
Advantageously, the conventional logic synthesis techniques employed for optimizing these don""t care states in order to reduce leakage power may be used to reduce area, improve circuit performance, and sometimes to reduce switching power. Thus, simultaneous optimization for several different objectives may be attempted. These may be combined by taking a weighted sum of the affect of the change on the various objective functions (e.g., K1*delta-area+K2*delta-switch-power+K3*delta-leakage-power) and choosing optimizations which give the best improvement in this weighted sum. Such cost-based changes may also be subject to constraints, e.g., make the change which gives the best improvement in the weighted objective function sum given above, as long as no net slack goes below some threshold value.